A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatch

Author

Zare-Hoseini, Hashem ; Shoaei, Omid ; Kale, Izzet

Author_Institution

Dept. of Electron. Syst., Westminster Univ., London, UK

fYear

2005

fDate

23-26 May 2005

Firstpage

1409

Abstract

A new multiply-by-two gain-stage (MBT-GS)(×2) is presented in which the gain-sensitivity to the capacitors´ mismatches is suppressed. Using one operational amplifier (op-amp) in three phases, a gain of two, which is not highly influenced by the mismatches between the capacitors, is achieved. An analytical study of the architecture is presented followed by some Monte-Carlo simulations using a generic 0.6 μm CMOS technology in HSPICE. Simulations clearly show the reduction of the matching-requirements in the new architecture.

Keywords

CMOS integrated circuits; analogue multipliers; analogue-digital conversion; integrated circuit design; mixed analogue-digital integrated circuits; network analysis; operational amplifiers; 0.6 micron; CMOS technology; HSPICE; capacitor-mismatch; enhanced immunity; high resolution analog to digital converters; multiply-by-two gain-stage; op-amp; operational amplifier; pipelined ADC; Analog integrated circuits; Analog-digital conversion; CMOS technology; Capacitors; Digital signal processing; Energy consumption; Operational amplifiers; Sampling methods; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464861

Filename

1464861