New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination

We propose a novel common subexpression elimination (CSE) method to be used for the VLSI design of a multiplierless finite impulse response (FIR) filter with a small number of adders and registers. The proposed method is an efficient way to reduce the function blocks using horizontal and vertical CSE. The FIR filters were synthesized from Verilog HDL code. Area and critical path values were evaluated for the 0.35 μm standard CMOS library. Compared with previous CSE techniques, the presented approach can save from a minimum of 0.8% up to a maximum 21.5% of gate area. Also, the critical path of the proposed method is an average of 3.2% or 17.6% shorter than those of other methods.