Title :
Simulation of grain-boundary induced vth variability in stackable NAND flash using a Voronoi approach
Author :
Ching-Wei Yang ; Shao-Heng Chao ; Pin Su
Author_Institution :
Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
Oct. 31 2012-Nov. 2 2012
Abstract :
In this work, we employ a novel Voronoi approach to simulate the impact of trap states in the poly-Si channel. Using this method, we investigate the grain boundary induced threshold voltage variability in stackable NAND flash memories. Our study indicates that considering the randomized shape and location of grain boundaries is crucial to the modeling and simulation of these devices.
Keywords :
NAND circuits; flash memories; grain boundaries; Voronoi approach; grain boundaries; grain boundary induced threshold voltage variability; poly-Si channel; randomized shape; stackable NAND flash memories; trap states; Flash memories; Fluctuations; Grain boundaries; Grain size; Logic gates; Silicon; Standards; BE-SONOS; Grain boundary; Voronoi; polycrystalline silicon; stackable NAND flash; variability;
Conference_Titel :
Non-Volatile Memory Technology Symposium (NVMTS), 2012 12th Annual
Conference_Location :
Singapore
Print_ISBN :
978-1-4673-2847-0
DOI :
10.1109/NVMTS.2013.6632851
