Use of embedded scheduling to compile VHDL for effective parallel simulation

This paper describes VHDL compilation techniques, embodied in the Auriga compiler, which facilitate parallel or distributed simulation by embedding evaluation scheduling in the emitted code. Unlike earlier but related cycle-driven techniques which map VHDL into simpler temporal semantics, the techniques described here preserve VHDL´s full temporal semantics. Experimental results indicate effective simulation acceleration using as many as 16 processors. Ongoing work involves evaluation with much larger models and machine configurations