A reconfigurable pipelined deblocking filter for H.264/AVC

This paper describes an efficient hardware architecture of the deblocking filter in H.264/AVC. The presented pipeline can reconfigure data-paths of various filtering modes in the deblocking filter. The size of on-chip SRAM is reduced with the edge processing order parallelizing two filters. We propose a novel pipelined data-path for the vertical filter to remove the transpose buffer between the horizontal and vertical edges. Maximum operating frequency of 200 Mhz is achieved with a relatively low memory usage.