DocumentCode :
3543311
Title :
Origin of transient Vth shift after erase and its impact on 2D/3D structure charge trap flash memory cell operations
Author :
Jong Kyung Park ; Dong-Il Moon ; Yang-Kyu Choi ; Seok-Hee Lee ; Ki-Hong Lee ; Seung Ho Pyi ; Byung Jin Cho
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
fYear :
2012
fDate :
10-13 Dec. 2012
Abstract :
The mechanism of transient Vth shift after erase is studied in detail. It is concluded that the main mechanism is hole redistribution in the charge trap layer. A new erase scheme is proposed and demonstrated to reduce transient Vth shift. The impact of transient Vth shift on the 3D charge trap device is investigated, as well.
Keywords :
flash memories; three-dimensional integrated circuits; transient analysis; 2D-3D structure charge trap flash memory cell operations; 3D charge trap device; charge trap layer; erase scheme; hole redistribution; transient voltage shift mechanism; Charge carrier processes; Dielectrics; Flash memory; Logic gates; Nanoscale devices; Silicon; Transient analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0163-1918
Print_ISBN :
978-1-4673-4872-0
Electronic_ISBN :
0163-1918
Type :
conf
DOI :
10.1109/IEDM.2012.6478964
Filename :
6478964
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3543311
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