WBR - word- and block-level hard error repair for memories

Many existing semiconductor memories face major problems concerning yield, reliability, testability, and manufacturability as the feature size decreases. In order to overcome these issues, new memory technologies are being developed. The greatest attention is paid to solid-state, non-volatile memories which are expected to meet the challenging demands of upcoming low-cost, low-power, and high-performance systems. However, despite all advantages which they offer, emerging non-volatile memories introduce challenges which have to be addressed and solved. One of the biggest obstacles preventing them from wider implementation are permanent faults which can occur right after production or during memory operational time. In order to mitigate the mentioned problem a novel memory repair approach, called WBR, has been invented. It is based on replacing defective data blocks with spare ones for every memory block separately. Repair procedures implemented in the WBR can be applied on memory word- and block-levels offering different repair speeds and correction capabilities. In comparison to recent solutions such as SAFER and ECP, WBR provides better memory lifetime improvement for small memory word sizes and achieves comparable results for wider memory words. In contrast to the state-of-the-art techniques, WBR can be applied to word sizes as small as 16 bits imposing less than 12.5% of additional bit overhead. The WBR can be implemented purely in hardware, e.g. in form of a memory controller. It is complementary to existing wear-leveling techniques, and it can be used in the recently-proposed PAYG framework.