Title :
Comparison of novel punch-through diode (NPN) selector with MIM selector for bipolar RRAM
Author :
Deshmukh, S. ; Mandapati, R. ; Lashkare, S. ; Borkar, A. ; Srivinasan, V.S.S. ; Lodha, Saurabh ; Ganguly, Utsav
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, Mumbai, India
fDate :
Oct. 31 2012-Nov. 2 2012
Abstract :
Recently, we have experimentally demonstrated a bipolar RRAM selector based on punch-through diode using an NPN stack by Si epitaxy (NPN selector). Historically, Metal-Insulator-Metal (MIM) selector has been a promising candidate as a bipolar RRAM selector due to low processing temperature which may enable back-end compatible stacked RRAM. In this report, we present an electrical performance comparison of the two technologies. NPN selector performance is obtained from experimentally calibrated TCAD simulations. A simple Fowler Nordheim (FN) and Direct Tunneling (DT) based model of MIM selector is chosen to evaluate performance (on-current, on-voltage and on/off current ratio). We show that MIM requires excess voltage for same on-off current ratio compared to NPN which undesirably increases RRAM array power consumption. Conversely, for the same operational voltage MIM selector has poorer on/off current ratio. Lower off-current capability enables NPN selectors to serve larger array sizes for comparable array leakage and consequently power loss.
Keywords :
MIM devices; leakage currents; performance evaluation; power aware computing; random-access storage; semiconductor device models; semiconductor diodes; technology CAD (electronics); tunnelling; DT-based model; FN-based model; Fowler Nordheim-based model; MIM selector; NPN selector performance evaluation; NPN stack; RRAM array power consumption; TCAD simulations; array leakage; back-end compatible stacked RRAM; bipolar RRAM selector; direct tunneling-based model; electrical performance comparison; metal-insulator-metal selector; off-current capability; on-off current ratio; operational voltage; punch-through diode selector; silicon epitaxy; Arrays; Electric fields; Insulators; Materials; Memory management; Power dissipation; Tunneling;
Conference_Titel :
Non-Volatile Memory Technology Symposium (NVMTS), 2012 12th Annual
Conference_Location :
Singapore
Print_ISBN :
978-1-4673-2847-0
DOI :
10.1109/NVMTS.2013.6632861