A Double Data Rate (DDR) architecture for OFDM based wireless consumer devices

The creation of OFDM based wireless personal area networks (WPANs) has allowed high bit-rate wireless communication devices suitable for streaming high definition video between consumer products as demonstrated in wireless-USB. However, these devices need high clock rates, particularly for the OFDM sections resulting in high silicon cost and high electrical power. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a double data rate (DDR) architecture to reduce the OFDM input and output clock rate by a factor of 2. The architecture has been implemented and tested for wireless-USB (ECMA-368) resulting in a maximum clock of 264 MHz instead of 528 MHz existing anywhere on the die.