Cascaded double-stage configuration for high-performance broadband amplification in CMOS

A high performance distributed amplifier (DA) based on the cascaded double-stage configuration is presented. Theoretical performance analysis, using three performance vectors - gain, bandwidth, and noise factor - is first conducted for the generalized m-cascaded n-stage DA. The analysis result is then exploited to enable comparison between three specific DA configurations that lend themselves to practice, including the classical DA, the cascaded single-stage DA (CSDA) and the cascaded double-stage DA (CDDA). The superiority of the double-stage configuration as indicated by the theoretical discussion is verified through simulations of gigahertz-range amplifiers with a 15dB gain using a 0.25μm 2.5V CMOS process. This shows that the CDDA outperforms the DA and the CSDA by more than a factor of 1.6 and 3.0 respectively.