Title :
Electrical performances of junctionless-FETs at the scaling limit (LCH = 3 nm)
Author :
Migita, S. ; Morita, Yusuke ; Masahara, M. ; Ota, Hiroyuki
Author_Institution :
Collaborative Res. Team Green Nanoelectron. Res. Center, AIST, Tsukuba, Japan
Abstract :
Junctionless-FETs (JL-FET) with extremely short channel length (LCH = 3 nm) were fabricated using anisotropic wet etching of SOI substrate, and superior transfer characteristics are demonstrated. Experimental results and simulation study predict that ultra-low voltage CMOS can be constructed using N- and P-type JL-FETs with single work function metal gate. Furthermore, it is cleared that carrier velocity in the short channel JL-FET is approaching to the injection velocity.
Keywords :
CMOS integrated circuits; etching; field effect transistors; silicon-on-insulator; SOI substrate; anisotropic wet etching; carrier velocity; electrical performances; injection velocity; n-type JL-FET; p-type JL-FET; scaling limit; short channel junctionless-FET; single work function metal gate; size 3 nm; transfer characteristics; ultra-low voltage CMOS; Fabrication; Hafnium compounds; Logic gates; Silicon; Temperature dependence; Wet etching;
Conference_Titel :
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4872-0
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2012.6479006
