Title :
300 K operating full-CMOS integrated Single Electron Transistor (SET)-FET circuits
Author :
Deshpande, V. ; Wacquez, R. ; Vinet, M. ; Jehl, Xavier ; Barraud, S. ; Coquand, R. ; Roche, B. ; Voisin, B. ; Vizioz, C. ; Previtali, B. ; Tosti, L. ; Perreau, P. ; Poiroux, T. ; Sanquer, Marc ; De Salvo, B. ; Faynot, O.
Author_Institution :
LETI, CEA, Grenoble, France
Abstract :
We demonstrate the first Single Electron Transistor (SET) with high-k/metal gate operating at room temperature (at VD=0.9 V) cointegrated with fully depleted SOI (FDSOI) MOSFET (with 20 nm gate length) to realize a hybrid SET-FET circuit. Our resulting circuit exhibits typical SET oscillations upto record milliampere range. We also demonstrate a SET-FET based Negative Differential Resistance (NDR) device with 104 peak-valley-current-ratio and also a literal gate for multivalued logic applications.
Keywords :
CMOS logic circuits; MOSFET; circuit oscillations; high-k dielectric thin films; multivalued logic circuits; negative resistance devices; silicon-on-insulator; single electron transistors; FDSOI MOSFET; NDR device; SET oscillations; SET-FET-based negative differential resistance device; full-CMOS integrated SET-FET circuits; full-CMOS integrated single electron transistor-FET circuits; fully depleted SOI MOSFET; high-k/metal gate transistor; hybrid SET-FET circuit; multivalued logic applications; temperature 293 K to 298 K; temperature 300 K; CMOS integrated circuits; Field effect transistors; Logic gates; Nanoscale devices; Oscillators; Silicon; Single electron transistors;
Conference_Titel :
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4872-0
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2012.6479007
