Title :
Enhancing the efficiency of cluster voltage scaling technique for low-power application
Author :
Amelifard, Behnam ; Afzali-Kusha, Ali ; Khadernzadeh, A.
Author_Institution :
Low-Power High-Performance Nanosystems Lab., Univ. of Tehran, Iran
Abstract :
In this paper, a scheme for power reduction based on cluster voltage scaling (CVS) for gate-level design of the VLSI circuits is presented. To increase the power reduction efficiency of the previous CVS techniques, a new low power level-shifter is utilized in the circuit. In addition, the concept of transistor ordering has been used to further reduce the power consumption. This technique shows an average improvement of 7% compared to the previous CVS circuits. The impact of CVS and its modified version on the reduction of short-circuit and leakage power are also discussed.
Keywords :
CMOS integrated circuits; VLSI; electrodes; integrated circuit design; integrated circuit metallisation; low-power electronics; CMOS; CVS; VLSI circuits; cluster voltage scaling; gate-level design; leakage power reduction; low power level-shifter; low-power application; power consumption; power reduction efficiency; short-circuit power reduction; transistor ordering; Capacitance; Delay; Dynamic voltage scaling; Energy consumption; Frequency; Laboratories; Power dissipation; Semiconductor device modeling; Switching circuits; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464925
