A low dynamic power and low leakage power CMOS square-root circuit

To reduce drastically the dynamic power (P_AT) and the leakage power (P_ST), while increasing the operating speed of a CMOS square-root (SR) circuit, a new SR algorithm and a self-controllable-voltage-level (SVL) circuit, consisting of a single CMOS switch, have been developed. They can not only drastically decrease the number of gates (G_c) in the critical path and the total number of logic gates (G), but also considerably reduce the leakage power. G_c and G of the new 8-bit, 0.16-μm CMOS SR circuit are greatly reduced to 30 and 97, 50.0% and 51.3%, respectively, of those of a conventional SR circuit. Thus, the maximum operating frequency (f_c) of the new SR circuit at a supply voltage (V_DD) of 1.5 V is 581 MHz, 1.62 times faster than the 358 MHz of the conventional SR circuit. P_AT of the new SR circuit, at f_c of 200 MHz and V_DD of 1.5 V, is reduced to 309 μW, 54.3% of the 569 μW of the conventional SR circuit. P_ST of the new SR circuit is only 8.8 nW, 1.36% of the 647 nW of the conventional SR circuit.