A 32nm SRAM reliability macro for recovery free evaluation of NBTI and PBTI

Author

Jain, Paril ; Paul, A. ; Xiaofei Wang ; Kim, Chul Han

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA

fYear

2012

fDate

10-13 Dec. 2012

Abstract

A scalable test structure for recovery free evaluation of the impact of NBTI and PBTI on read/write operation in a SRAM macro has been developed. A novel non-invasive methodology keeps the stress interrupts for measurements within a few microseconds, preventing unwanted BTI recovery, while providing a parallel stress-measure capability on 32kb sub-arrays. Measurement results in a 32nm high-κ/metal-gate silicon-on-insulator process show that proposed schemes provides 35mV better accuracy in read V_MIN and 10X accuracy in BFR.

Keywords

SRAM chips; integrated circuit reliability; integrated circuit testing; stress analysis; NBTI; SRAM reliability macro; and PBTI; high-κ-metal-gate silicon-on-insulator process; negative bias temperature instability; parallel stress-measure capability; positive bias temperature instability; read-write operation; recovery free evaluation; scalable test structure; size 32 nm; storage capacity 32 Kbit; stress interrupts; unwanted BTI recovery; voltage 35 mV; Arrays; Random access memory; Reliability; Stress; Stress measurement; System-on-chip; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2012 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4673-4872-0

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2012.6479014

Filename

6479014