Author :
Park, Soojin ; Kim, Heonhwan ; Choo, M. ; Noh, Junyong ; Sheri, A. ; Jung, Sanghyuk ; Seo, Kazuyuki ; Park, Jongho ; Kim, Sungho ; Lee, Wei-Jen ; Shin, Jeyong ; Lee, Daewoo ; Choi, GanHo ; Woo, Jiyong ; Cha, Elizabeth ; Jang, Jin ; Park, C. ; Jeon, Moon-G
Abstract :
Feasibility of a high speed pattern recognition system using 1k-bit cross-point synaptic RRAM array and CMOS-based neuron chip has been experimentally demonstrated. Learning capability of a neuromorphic system comprising RRAM synapses and CMOS neurons has been confirmed experimentally, for the first time.
Keywords :
CMOS memory circuits; neural chips; pattern recognition; random-access storage; CMOS-based neuron chip; RRAM-based synapse; cross-point synaptic RRAM array; high speed pattern recognition system; neuromorphic system; pattern recognition function; storage capacity 1 Kbit; Arrays; CMOS integrated circuits; Neuromorphics; Neurons; Semiconductor device modeling; Testing; Training;
