DocumentCode
3543817
Title
A power-aware signed 2-dimensional bypassing multiplier for video/image processing
Author
Sung, Gang-Neng ; Lu, Yu-Cheng ; Wang, Chua-Chin
Author_Institution
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fYear
2010
fDate
9-13 Jan. 2010
Firstpage
511
Lastpage
512
Abstract
This paper presents a power-aware signed digital multiplier design by taking advantage of a 2-dimensional bypassing method dedicated for local multiplications widely used in FFT/IFFT operations of video/image processing. The proposed low power multiplier is carried out by Baugh-Wooley algorithm using novel 2-dimensional bypassing cells. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally (row) partial product or the vertically (column) operand is zero.
Keywords
fast Fourier transforms; logic design; multiplying circuits; video signal processing; 2D bypassing cells; 2D bypassing multiplier; Baugh-Wooley algorithm; FFT-IFFT computation; image processing; power-aware signed digital multiplier; video processing; Adders; Circuits; Digital arithmetic; Digital filters; Digital signal processing; Digital signal processors; Energy efficiency; Image processing; Power dissipation; Signal processing algorithms; Baugh-Wooley; FFT/IFFT computations; bypassing; low power multiplier; partial product;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ICCE), 2010 Digest of Technical Papers International Conference on
Conference_Location
Las Vegas, NV
Print_ISBN
978-1-4244-4314-7
Electronic_ISBN
978-1-4244-4316-1
Type
conf
DOI
10.1109/ICCE.2010.5418863
Filename
5418863
Link To Document