A novel VLSI architecture for VBSME in MPEG-4 AVC/H.264

Author

Wei, Cao ; Gang, Mao Zhi

Author_Institution

Microelectron. Center, Harbin Inst. of Technol., China

fYear

2005

fDate

23-26 May 2005

Firstpage

1794

Abstract

Variable block-size motion estimation (VBSME) is adopted in the MPEG-4 AVC/H.264 standard. In this paper, we proposed a new reconfigurable VLSI architecture for VBSME with FBMA to support a "meander"-like scan format for a high data reuse of the search area. The architecture can reuse the smaller blocks\´ sum of absolute differences to calculate 41 motion vectors (MVs) of a 16×16 block in parallel. Our design was implemented with 0.25 μm CMOS technology. Under a clock frequency of 52 MHz, the architecture allows the real-time processing of 720×576 at 30 fps in a search range [-6, +15].

Keywords

CMOS integrated circuits; VLSI; motion estimation; parallel architectures; reconfigurable architectures; video coding; 0.25 micron; 414720 pixel; 52 MHz; 576 pixel; 720 pixel; CMOS; FBMA; MPEG-4 AVC/H.264; VBSME; meander-like scan format; parallel motion vector calculation; real-time processing; reconfigurable VLSI; search area data reuse; search range; sum of absolute differences; variable block-size motion estimation; Automatic voltage control; Broadcasting; CMOS technology; Clocks; Frequency; Integrated circuit interconnections; MPEG 4 Standard; Microelectronics; Motion estimation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464957

Filename

1464957