Title :
A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits
Author :
Clark, Lawrence T. ; Zhao, Dongbin ; Bakhishev, T. ; Ahn, Hyo-Sung ; Boling, Edward ; Duane, M. ; Fujita, Kinya ; Gregory, P. ; Hoffmann, T. ; Hori, Muneo ; Kanai, D. ; Kidd, David ; Lee, Sang-Rim ; Liu, Yanbing ; Mitani, Jun ; Nagayama, J. ; Pradhan, Sub
Author_Institution :
SuVolta, Inc., Los Gatos, CA, USA
Abstract :
65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (VT) variation, lower supply voltage (VCC), enhanced body effect and IEFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower VDD, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.
Keywords :
MOSFET; current mirrors; system-on-chip; DDC transistors; NMOS transistor; PMOS transsistor; amplifier gain; analog circuits; current mirror mismatch; deeply depleted channel transistor; digital circuits; enhanced body effect; halo-free undoped epitaxial channel; highly integrated SoC process; reduced threshold voltage variation; size 65 nm; Analog circuits; Logic gates; MOS devices; Mirrors; Process control; Random access memory; Transistors;
Conference_Titel :
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4872-0
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2012.6479042
