Title :
Design and Analysis of a Mesh-based Wireless Network-on-Chip
Author :
Hu, Wen-Hsiang ; Wang, Chifeng ; Bagherzadeh, Nader
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Irvine, CA, USA
Abstract :
Network-on-chip (NoC) architecture is regarded as a solution for future on-chip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long distance communication among processing elements. To solve these limitations, we employed on-chip wireless communication as express links for transferring data so that transfer latency can be reduced. A hybrid NoC architecture utilizing both wired and wireless communication approaches is proposed in this paper. We also devised a deadlock free routing algorithm that is able to make efficient use of the incorporated wireless links. Moreover, simulated annealing optimization techniques were applied to find optimal locations for wireless routers. Cycle-accurate simulation results showed a significant improvement in transfer latency. Area and power consumption analysis demonstrates the feasibility of our proposed NoC architecture.
Keywords :
integrated circuit interconnections; network routing; network-on-chip; power consumption; simulated annealing; deadlock free routing; hybrid NoC architecture; incorporated wireless links; mesh-based wireless network-on-chip; multihop long distance communication; on-chip interconnects; power consumption; simulated annealing optimization; transfer latency; transferring data; CMOS integrated circuits; Computer architecture; Power demand; Routing; System recovery; System-on-a-chip; Wireless communication; Wireless network-on-chip; network-on-chip; onchip interconnection network;
Conference_Titel :
Parallel, Distributed and Network-Based Processing (PDP), 2012 20th Euromicro International Conference on
Conference_Location :
Garching
Print_ISBN :
978-1-4673-0226-5
DOI :
10.1109/PDP.2012.19