A three-level toggle-avoid bus signaling scheme

Coupling capacitances between bus lines are dominant in deep-submicron technologies, as a result, both power dissipation and worst-case delay are increased due to coupling transitions. Based on the observation that the toggling sequences 01->10 or 10->01 between two adjacent lines result in four times more coupling energy than other coupling events, we propose a toggle-avoid signaling scheme. By applying a three-level signaling on buses with a choice for representing logic "1", toggling events are reduced with no extra bus lines. We achieve 32% total power savings and 40% worst-case delay reduction with a small power overhead.