A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch

Author

Kim, Tae-Hyoung ; Cho, Uk-Rae ; Byun, Hyun-Geun

Author_Institution

Memory Div., Samsung Electron., Kyeonggi-Do, South Korea

fYear

2005

fDate

23-26 May 2005

Firstpage

1847

Abstract

This paper describes memory interface circuits applicable to multi Gbit/s/pin chip-to-chip communication. To obtain the high linearity characteristics of the off-chip drivers (OCD) and the on-die terminators (ODT), a novel circuit structure is proposed. The linearity error of the designed OCD and ODT is 4.7% and 1.7% respectively when measured between 0.2V and 1V. The pull-up and pull-down impedance mismatch is reduced by adding a compensation impedance unit. The maximum pull-up and pulldown mismatch is 0.5 bit. An impedance update scheme without training sequence is designed to guarantee the signal integrity of the first data. The valid data window is 418ps at 2Gbit/s, Vref ±150mV. The proposed circuits are fabricated with 0.1μm dual-oxide CMOS process technology.

Keywords

CMOS memory circuits; driver circuits; impedance matching; 0.1 micron; 0.2 to 1 V; 1.2 V; 2 Gbit/s; chip-to-chip communication; compensation impedance unit; dual-oxide CMOS process; impedance update scheme; linearity; memory interface circuits; off-chip drivers; on-die terminators; pull-down impedance mismatch; pull-up impedance mismatch; Automatic control; CMOS process; Driver circuits; Impedance; Linearity; MOSFETs; Reflection; Resistors; Transmission lines; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464970

Filename

1464970