Title :
InAs-Si heterojunction nanowire tunnel diodes and tunnel FETs
Author :
Riel, Heike ; Moselund, Kirsten ; Bessire, C. ; Bjork, M.T. ; Schenk, Andreas ; Ghoneim, H. ; Schmid, Heinz
Author_Institution :
IBM Res. - Zurich, Zurich, Switzerland
Abstract :
In this paper we present vertical tunnel diodes and tunnel FETs (TFETs) based on III-V-Si nanowire heterojunctions. We experimentally demonstrate InAs-Si Esaki tunnel diodes with record high currents of 6 MA/cm2 at 0.5 V in reverse bias. Furthermore, we have fabricated vertical InAs-Si nanowire TFETs with gate-all-around architecture and high-k dielectrics. The InAs-Si combination allows achieving high Ion/Ioff ratios above 106, with Ion of 2.4 μA/μm and an inverse subthreshold slope of 150 mV/dec over three decades. The achieved improvements can be attributed to increased nanowire doping and Ni alloying of the top contact. The results indicate the benefits of the InAs-Si material system combining the possibility of achieving high Ion with high Ion/Ioff ratio.
Keywords :
III-V semiconductors; elemental semiconductors; field effect transistors; high-k dielectric thin films; indium alloys; nanowires; nickel alloys; silicon; tunnel diodes; tunnel transistors; Esaki tunnel diodes; InAs-Si; Ni; TFET; gate-all-around architecture; heterojunction nanowire tunnel diodes; high-k dielectrics; inverse subthreshold slope; material system; nanowire doping; reverse bias; top contact; tunnel FET; vertical tunnel diodes; voltage 0.5 V; Annealing; Doping; Heterojunctions; Logic gates; Silicon; Temperature measurement; Tunneling;
Conference_Titel :
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4872-0
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2012.6479056
