Title :
A 5V charge pump in a standard 1.8-V 0.18-μm CMOS process
Author :
Hasan, Tawfique ; Lehmann, Torsten ; Kwok, Chee Yee
Author_Institution :
Sch. of Electr. Eng. & Telecommun., New South Wales Univ., Sydney, NSW, Australia
Abstract :
A new high voltage tolerant charge pump structure, designed with a standard low voltage CMOS process, is presented. This fully integrated charge pump design uses a symmetrical structure and can be scaled to achieve higher voltages up to a certain limit. The design is based on a standard 1.8-V 0.18-μm CMOS process without the high voltage option. Simulation result shows an output voltage of 5.12 V with a 250 kΩ load and an operating frequency of 2.5 MHz. The efficiency of the circuit is 77% and satisfies typical voltage stress related reliability requirements for low voltage CMOS devices.
Keywords :
CMOS integrated circuits; electric potential; integrated circuit design; integrated circuit reliability; low-power electronics; semiconductor device reliability; voltage multipliers; 0.18 micron; 1.8 V; 2.5 MHz; 5.12 V; circuit efficiency; high voltage tolerant charge pump structure; low voltage CMOS devices; operating frequency; voltage stress related reliability; Breakdown voltage; CMOS process; CMOS technology; Capacitors; Charge pumps; Electric breakdown; Integrated circuit reliability; Low voltage; Stress; Switches;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464983
