A low voltage CMOS multiplier for high frequency equalization

This paper describes the design of a low power 1.2V CMOS multiplier for 10 Gbit/s continuous time finite impulse response (FIR) filter. The multiplier is based on a low noise amplifier (LNA) architecture and has variable gain, which is directly controlled by a 5 bit digital word. This direct control removes the need for a digital to analog converter to set the gain of the multiplier. The 5 bit control word allows 32 possible gain settings from a minimum gain of -1 to a maximum gain +1 with linearity errors less than 1%. The gain is achieved by switching in various combinations of binary weighted gain stages. To achieve negative gain, a swap switch is used which reduces the number of gain stages required and also reduces the parasitic load on the summing node. The circuit requires 1.9 mA of current and has a post-extracted bandwidth of 7.6 GHz.