DocumentCode
3544150
Title
A low current consumption CMOS latched comparator for body-implanted chip
Author
Kiyoyama, K. ; Onoda, M. ; Tanaka, Y.
Author_Institution
Nagasaki Inst. of Appl. Sci., Japan
fYear
2005
fDate
23-26 May 2005
Firstpage
1940
Abstract
The paper presents a very low-current consumption latched comparator, for use in a medical application, as a component of a delta-sigma (ΔΣ) modulator, which takes advantage of the low gate-source voltage by operating in the sub-threshold region. The comparator has been designed using 0.35-μm standard CMOS technology, operating with a 1.5 V power supply. The current consumption of the comparator achieved was less than 150 nA in a post-layout simulation.
Keywords
CMOS integrated circuits; biomedical electronics; comparators (circuits); delta-sigma modulation; integrated circuit design; network analysis; 0.35 micron; 1.5 V; 150 nA; CMOS latched comparator; body-implanted chip; current consumption; delta-sigma modulator; gate-source voltage; implanted ECG sensor; Biomedical equipment; CMOS technology; Delta modulation; Electric variables measurement; Electrocardiography; Frequency measurement; Medical services; Power measurement; Power supplies; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464993
Filename
1464993
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