DocumentCode :
3544200
Title :
kT/C constrained optimization of power in pipeline ADCs
Author :
Lin, Yu ; Katyal, Vipul ; Geiger, Randall ; Schlarmann, Mark
Author_Institution :
Dept. Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
fYear :
2005
fDate :
23-26 May 2005
Firstpage :
1968
Abstract :
This paper presents a method to optimize the power consumption of a pipelined ADC with kT/C noise constraint. The total power dependence on capacitor scaling and stage resolution is investigated. With eight different capacitor scaling functions, near-optimal solution can be obtained. For a 12-bit pipeline ADC, the power decreases with effective number of bits per stage. This method can be easily extended to other resolution pipeline ADC.
Keywords :
analogue-digital conversion; capacitors; circuit optimisation; integrated circuit noise; pipeline processing; power consumption; capacitor scaling; constrained power optimization; kT/C noise constraint; near-optimal solution; pipelined ADC; power dependence; stage resolution; Capacitance; Capacitors; Constraint optimization; Energy consumption; Pipelines; Power dissipation; Signal resolution; Signal to noise ratio; Switches; Switching circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
Type :
conf
DOI :
10.1109/ISCAS.2005.1465000
Filename :
1465000
Link To Document :
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