A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques

This paper exploits the possibility to merge an operational amplifier-sharing technique into a switched-operational amplifier configuration. In a switched-operational amplifier based design, the capacitors connected to the operational amplifier output are not switchable, therefore the insertion of the operational amplifier-sharing technique demands two output stages within an operational amplifier. A 1-V 9-bit 2.5-Msample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.