Full calibration digital techniques for pipeline ADCs

This paper presents a new digital algorithm for full calibration of pipeline ADC with digital redundancy. The proposed algorithm corrects both the MDAC gain error of the stage under calibration (SUC) and its nonlinear errors. It is based on the modulation of the analogue output of the SUC using a digital control signal to introduce a constant displacement in the references of the comparators in the SUC sub-ADC without reduction of the input dynamic rate. This process can be performed without interruption of the conversion (background mode) including a digital pseudo-random number generator (RNG). The foreground implementation of this algorithm uses a DC calibration stimulus which relaxes the hardware requirements.