• DocumentCode
    3544297
  • Title

    VLSI architecture design for reconfigurable block size motion estimation

  • Author

    Li, Peng ; Tang, Hua

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Duluth, MN, USA
  • fYear
    2010
  • fDate
    9-13 Jan. 2010
  • Firstpage
    439
  • Lastpage
    440
  • Abstract
    This paper presents a VLSI architecture to support full-search motion estimation with reconfigurable block size, which is well needed in video based surveillance applications. Experiment results show that the proposed architecture achieves the flexibility of adjustable block size at the expense of only 5% hardware overhead compared to the traditional design.
  • Keywords
    VLSI; logic design; motion estimation; video coding; video surveillance; VLSI architecture design; full-search motion estimation; reconfigurable block size; video based surveillance; video coding; Motion estimation; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Consumer Electronics (ICCE), 2010 Digest of Technical Papers International Conference on
  • Conference_Location
    Las Vegas, NV
  • Print_ISBN
    978-1-4244-4314-7
  • Electronic_ISBN
    978-1-4244-4316-1
  • Type

    conf

  • DOI
    10.1109/ICCE.2010.5418945
  • Filename
    5418945
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3544297