DocumentCode
3544318
Title
An integration path for gate-first UTB III-V-on-insulator MOSFETs with silicon, using direct wafer bonding and donor wafer recycling
Author
Czornomaz, L. ; Daix, N. ; Caimi, D. ; Sousa, M. ; Erni, R. ; Rossell, M.D. ; El-Kazzi, M. ; Rossel, C. ; Marchiori, C. ; Uccelli, Emanuele ; Richter, Maximilian ; Siegwart, H. ; Fompeyrine, J.
Author_Institution
IBM Zurich Res. Lab., Rüschlikon, Switzerland
fYear
2012
fDate
10-13 Dec. 2012
Abstract
In this work we demonstrate for the first time that the excellent thermal stability of ultra-thin body (UTB) III-V heterostructures on silicon provides a path for the cointegration of self-aligned In0.53Ga0.47As MOSFETs with silicon. We first demonstrate that the transfer of high-quality InGaAs / InAlAs heterostructures (tch <; 10 nm) can be achieved by direct wafer bonding and hydrogen-induced thermal splitting, and that the donor wafer can be recycled for a cost-effective process. The thermal stability of the bonded layer enables to integrate UTB III-V MOSFETs at 500 nm pitch using a gate-first flow featuring raised source/drain (S/D) grown at 600oC. The expected benefit of an UTB structure is benchmarked by comparing sub-threshold slope (SS) and drain-induced-barrier-lowering (DIBL) against state-of-the-art III-V-o-I or Tri-Gate FET data.
Keywords
MOSFET; thermal stability; wafer bonding; MOSFET; cost effective process; direct wafer bonding; donor wafer recycling; drain induced barrier lowering; gate first flow featuring raised source; hydrogen induced thermal splitting; integration path; subthreshold slope; thermal stability; ultra thin body; Indium gallium arsenide; Indium phosphide; Logic gates; MOSFETs; Silicon; Thermal stability;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location
San Francisco, CA
ISSN
0163-1918
Print_ISBN
978-1-4673-4872-0
Electronic_ISBN
0163-1918
Type
conf
DOI
10.1109/IEDM.2012.6479088
Filename
6479088
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