III-V gate-all-around nanowire MOSFET process technology: From 3D to 4D

Author

Gu, J.J. ; Wang, X.W. ; Shao, Jin ; Neal, A.T. ; Manfra, Michael J. ; Gordon, Roy G. ; Ye, Peide D.

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2012

fDate

10-13 Dec. 2012

Abstract

In this paper, we have experimentally demonstrated, for the first time, III-V 4D transistors with vertically stacked InGaAs nanowire (NW) channels and gate-all-around (GAA) architecture. Novel process technology enabling the transition from 3D to 4D structure has been developed and summarized. The successful fabrication of InGaAs lateral and vertical NW arrays has led to 4× increase in MOSFET drive current. The top-down technology developed in this paper has opened a viable pathway towards future low-power logic and RF transistors with high-density III-V NWs.

Keywords

III-V semiconductors; MOSFET; low-power electronics; nanowires; GAA architecture; III-V 4D transistors; III-V gate-all-around nanowire MOSFET process technology; InGaAs; MOSFET drive current; NW channels; RF transistors; gate-all-around architecture; high-density III-V NW; lateral NW arrays; low-power logic; top-down technology; vertical NW arrays; vertically stacked nanowire channels; Fabrication; Field effect transistors; Indium gallium arsenide; Indium phosphide; Logic gates; Measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2012 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4673-4872-0

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2012.6479091

Filename

6479091