Title :
Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective
Author :
Huichu Liu ; Cotter, Matthew ; Datta, Soupayan ; Narayanan, Vijaykrishnan
Author_Institution :
Dept. of Electr. Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
Sea-level soft error performance has been investigated for Si FinFET, III-V FinFET and III-V Heterojunction Tunnel FET in this paper. Transient error generation and transient current profiles in these devices have been evaluated using device simulation. Based on the critical charge extraction for each emerging device-based circuit, the electrical and latching window masking effects have been studied. Below 0.5V, III-V FinFET logic shows reduced soft error rate (SER) compared to Si FinFET. HTFET shows reduced SER for both SRAM and logic compared to Si and III-V FinFET over the evaluated voltage range of 0.3V-0.6V.
Keywords :
III-V semiconductors; MOSFET; FinFET logic; SRAM; critical charge extraction; device based circuit; device simulation; heterojunction tunnel FET; latching window masking effect; reduced soft error rate; sea level soft error performance; technology assessment; transient current profiles; transient error generation; voltage 0.3 V to 0.6 V; FinFETs; Latches; Neutrons; SRAM cells; Silicon; Transient analysis;
Conference_Titel :
Electron Devices Meeting (IEDM), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4872-0
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2012.6479103