DocumentCode :
3544451
Title :
Clock tree construction using gated clock cloning
Author :
Chen, Wun-Han ; Chang, Hsin-Hung ; Hung, Jui-Hung ; Hsieh, Tsai-Ming
Author_Institution :
Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chungli, Taiwan
fYear :
2012
fDate :
10-11 July 2012
Firstpage :
54
Lastpage :
58
Abstract :
Clock gating is one of the important techniques to achieve low power and small area in high-performance synchronous circuit design. In this paper, we propose a three-phase clock gating optimization methodology by using clustering and merging algorithm to construct a gated clock tree with minimal number of clock gating cells and buffers. In addition, according to the fan-out numbers of a clock gating cell, we derive a parameter γ that may be used to adjust the tradeoff between clock gating cell and buffer. The experimental results show that the number of clock gating cells and buffers reduced in each phase in our algorithm. Our solutions are better than greedy approach.
Keywords :
buffer circuits; clocks; logic circuits; logic design; low-power electronics; pattern clustering; buffers; clock gating cells; clock tree construction; clustering-merging algorithm; gated clock cloning techniques; greedy approach; high-performance synchronous circuit design; three-phase clock gating optimization methodology; Clocks; Cost function; Delay; Flip-flops; Logic gates; Synchronization; Time factors; clock gating; clock tree; setup time;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ASQED), 2012 4th Asia Symposium on
Conference_Location :
Penang
Print_ISBN :
978-1-4673-2687-2
Type :
conf
DOI :
10.1109/ACQED.2012.6320475
Filename :
6320475
Link To Document :
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