A low power high speed error correction code macro using complementary pass transistor logic circuit

Author

Wang, L.K. ; Chen, Howard H.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1997

fDate

7-10 Sep 1997

Firstpage

17

Lastpage

20

Abstract

This paper describes the design and implementation of the complementary pass transistor logic (CPL) circuit in a CMOS macro design. The power, speed and noise margin of pass-transistor logic circuits are evaluated and the transistor sizes are optimized for noise margin and circuit performance. This circuit has been successfully implemented in a 64-bit Error Correction Code (ECC) and parity checking macro in the IBM S/390 CMOS processor and significantly improves the power and speed of the ECC macro performance

Keywords

CMOS logic circuits; error correction codes; integrated circuit noise; logic design; 0.25 micron; 2.5 V; 64 bit; CMOS macro design; IBM S/390 CMOS processor; complementary pass transistor logic circuit; error correction code macro; high speed ECC macro; low power macro; noise margin; parity checking; CMOS logic circuits; Circuit noise; Circuit optimization; Error correction; Error correction codes; Hardware; Logic circuits; Power supplies; Power system protection; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International

Conference_Location

Portland, OR

ISSN

1063-0988

Print_ISBN

0-7803-4283-6

Type

conf

DOI

10.1109/ASIC.1997.616970

Filename

616970