Hardware-efficient computing architecture for motion compensation interpolation in H.264 video coding

The paper addresses a new computing architecture for motion compensation interpolation in the ITU-T H.264 video codec. In the H.264 standard, quarter-pixel interpolation is achieved by using a 6-tap horizontal or vertical FIR filter (for luminance) and a bilinear filter (for chrominance). However, the computing procedures are irregular, thus complicating their corresponding hardware implementation. We propose an alternative of using a 4-tap diagonal FIR filter for interpolation in luminance and a three-stage recursive algorithm to reduce the number of multiplications for interpolation in chrominance. Experiments and analysis show that our proposed algorithms cause negligible quality degradation in image PSNR performance and much more efficiency in hardware implementation.