DocumentCode
3544543
Title
A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications
Author
Sheng, Duo ; Chung, Ching-Che ; Lan, Jhih-Ci
Author_Institution
Dept. of Electr. Eng., Fu Jen Catholic Univ., New Taipei, Taiwan
fYear
2012
fDate
10-11 July 2012
Firstpage
123
Lastpage
127
Abstract
In this paper, a monotonic and low-power digitally controlled oscillator (DCO) with cell-based design for System-On-Chip (SoC) applications is presented. The proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Besides, based on the proposed two-level controlled interpolation structure, the proposed DCO can provide monotonic delay with low power consumption and low circuit complexity as compared with conventional approaches. Simulation results show that power consumption of the proposed DCO can be improved to 0.337mW (@1118MHz) with 0.82ps resolution. In addition, the proposed DCO can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.
Keywords
integrated circuit design; interpolation; low-power electronics; oscillators; system-on-chip; DCO; SoC applications; cascade-stage structure; cell-based design; frequency 1118 MHz; low circuit complexity; low power consumption; low-power digitally controlled oscillator; monotonic delay; power 0.337 mW; standard cells; system-on-chip; time 0.82 ps; two-level controlled interpolation structure; Clocks; Delay; Interpolation; Phase locked loops; Power demand; System-on-a-chip; Tuning; Digitally controlled oscillator (DCO); delay monotonicity; low power; portable; standard cells;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ASQED), 2012 4th Asia Symposium on
Conference_Location
Penang
Print_ISBN
978-1-4673-2687-2
Type
conf
DOI
10.1109/ACQED.2012.6320487
Filename
6320487
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