Analysis of system bus on SoC platform using TSV interconnection

Author

Cho, Kyoungrok ; Na, Hyeon-Seok ; Cho, Tae Won ; You, Younggap

Author_Institution

Coll. of Electr. & Comput. Eng., Chungbuk Nat. Univ., Cheongju, South Korea

fYear

2012

fDate

10-11 July 2012

Firstpage

227

Lastpage

231

Abstract

This paper proposes a latency model for a multi-layer system on chip (SoC) structure employing through silicon vias (TSVs). TSVs are used to interconnect multiple SoC chips stacked to form a three-dimensional (3-D) structure. The proposed latency model has been used to estimate the system performance. The performance estimation reflects the number of IPs connected to the system bus, data throughput and the number of masters in the system. The maximum throughput calculation results can be used to find the appropriate number of chips to be stacked during the 3-D multi-layer SoC system design process.

Keywords

integrated circuit design; system buses; system-on-chip; three-dimensional integrated circuits; 3D multilayer SoC system design process; SoC platform; TSV interconnection; data throughput; maximum throughput calculation; multilayer system on chip structure; multiple SoC chips; performance estimation; system bus; three-dimensional structure; through silicon vias; Bridge circuits; Clocks; IP networks; Silicon; System-on-a-chip; Through-silicon vias; Throughput; Latency model; SoC; system bus; through silicon via; throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design (ASQED), 2012 4th Asia Symposium on

Conference_Location

Penang

Print_ISBN

978-1-4673-2687-2

Type

conf

DOI

10.1109/ACQED.2012.6320506

Filename

6320506