Structural package and board design approach for System-on-Chip power delivery analysis

With the increasing complexity of circuit design, CPU and chipset electrical design target has changed and continue to be more stringent. Power delivery design is getting more challenging to ensure no device functional failure in low power and low cost product. Therefore, platform power delivery engineer is playing an essential role in implementing robust electrical solution. Despite of all these, there is a hidden challenge as System-on-Chip power delivery engineer does not have platform design detail for instance package stack-up and number of layer as well as platform size to initiate power delivery design. This urges the team to transform from traditional passive power delivery working model to more proactive role. This paper presents structural approach of platform parasitic estimation at early product definition phase and production design cycle phase. Accurate estimation of platform parasitic is important to enable early product power delivery involvement and BGA (Ball Grid Array) reduction that could facilitate product cost saving. The correlation of the estimated result and the simulated result is presented and further discussed in the study.