Design and Implementation of Automated Wave-Pipelined Circuit Using ASIC

Wave-pipelining enables a digital circuit to be operated at higher frequency. In the literature, only trial and error and manual procedures are adopted for the choice of the optimum value of clock and clock skew between the I/O registers of wave-pipelined circuits. The major contribution of this paper is the proposal for automating the above procedure for the ASIC implementation of wave-pipelined circuits using built in self test approach. This is studied by a multiplier using dedicated AND gate by adopting three different schemes: wave-pipelining, pipelining and non-pipelining. From the implementation results, it is verified that the wavepipelined multipliers are faster by a factor of 1.08 compared to the non-pipelined multipliers. The wavepipelined multiplier dissipates less power in the factor of 1.43 compared to the pipelined multiplier.