Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops

The paper presents analysis results on jitter transfer in delay-locked loops (DLLs). Using a z-domain model for re-circulating DLLs, two main jitter factors, jitter peaking and jitter accumulation, are calculated and it is shown that these two factors always exist and trade off with each other. Using a first or second order of low-pass filter as the loop filter reduces the high frequency jitter amplification. Meanwhile, low frequency jitter amplification could be decreased using a suitable band-pass filter after the delay line. The amount of jitter peaking is shown to be proportional to the tracking bandwidth and, therefore, the lock time, but the jitter accumulation factor is inversely proportional to the bandwidth of the DLL.