A Novel Architecture for an Efficient Implementation of Image Compression Using 2D-DWT

This paper presents the design and implementation of image compression using 2D DWT. Major contribution of this paper is an efficient architecture called modified flipping is proposed for the implementation of image compression using 2d DWT. The SOC approach is adopted for the implementation of 2D DWT on Altera Field Programmable Gate Arrays (FPGAs) based SOC CYCLONE II EP2C35F672C6 kits with NIOS-II soft-core processor. From the implementation results, it is verified that the proposed architecture increases the speed and reduces the number of logical elements and registers. A new multiplier algorithm called as Modified Baugh-Wooley pipelined constant coefficient multiplier (MBW-PKCM) is proposed for signed multiplication. Distributed Arithmetic architecture with constant coefficient multiplier is used to implement MBW multiplier. From the implementation results, it is concluded that the proposed Modified flipping Architecture (MFA) and MBW-PKCM reduce the hardware requirements, and the speed of the design is increased.