Title :
Design of wave-pipelined 900 MHz 16b ripple-carry adder using modified NPCPL
Author :
Choi, H. ; Hwang, S.H.
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Abstract :
Wave pipelining is a very efficient way to design high-throughput processing elements, but it requires accurate delay control. Hence, Normal Process Complementary Pass Transistor Logic (NPCPL) has been used in place of static CMOS logic which suffers delay variation depending on input combinations. However, conventional NPCPL has two problems in high speed wave-pipelining; insufficient driving capability and unbalanced loading. In this paper, we address the above problems and propose a new NPCPL architecture which overcomes those problems. We also show experimental results obtained from 16b ripple-carry adder using our proposed NPCPL in 0.8 μm technology that shows 900 MHz throughput
Keywords :
CMOS logic circuits; adders; pipeline arithmetic; 0.8 micron; 16 bit; 900 MHz; NPCPL architecture; Normal Process Complementary Pass Transistor Logic; delay control; driving; high speed CMOS logic; high-throughput processing element; load balancing; wave-pipelined ripple-carry adder; CMOS logic circuits; CMOS process; CMOS technology; Load management; Pipeline processing; Process design; Propagation delay; Throughput; Transistors; Voltage;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541930
