Title :
A novel approach for network on chip emulation
Author :
Genko, N. ; Atienza, D. ; De Micheli, G. ; Benini, L. ; Mendias, J.M. ; Hermida, R. ; Catthoor, F.
Author_Institution :
Stanford Univ., Palo Alto, CA, USA
Abstract :
Current systems-on-chip execute applications that demand extensive parallel processing. Networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoCs can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a range of solutions, as well as characterize quickly performance figures.
Keywords :
field programmable gate arrays; hardware-software codesign; logic testing; multiprocessor interconnection networks; network interfaces; system-on-chip; telecommunication network topology; FPGA; HW-SW NoC emulation; ad hoc topology; cycle accuracy; functional validation; network interfaces; network on chip emulation; parallel processing; systems-on-chip; Communication switching; Emulation; Field programmable gate arrays; Hardware design languages; Network topology; Network-on-a-chip; Packet switching; Silicon; Switches; Testing;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465100
