A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering

A computational digital-pixel-sensor (DPS) VLSI with on-chip image processing circuits has been developed. A 64×32 DPS array and versatile rank-order filtering circuits are implemented. A newly proposed block-readout architecture is employed in the DPS memory in order to resolve the interconnection bottleneck between sensors and processing units. The data from the sensor array are read out in blocks and processed on the chip. As a result, this architecture enhances the performance of bit-serial digital signal processing. The paper also presents a versatile rank-order filtering circuit. The proposed rank-order filtering algorithm and reversed rank-order filtering algorithm are merged and implemented in a simplified circuit. The pixel-parallel seamless scan of filtering operations has been successfully realized.