A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration

The performance of static CMOS circuits is superior in terms of power consumption and glitch reduction to dynamic circuits when the fan-in is small. We propose a new static dual edge-triggered flip-flop that incorporates no precharging and conditional discharging to reduce the switching activity at the internal node efficiently. Hence, the power dissipation is very much reduced. Based on simulation results derived from 0.18-μm CMOS technology, our proposed flip-flop consumes the least power regardless of the input data activity.