An efficient pass-transistor-logic synthesizer using multiplexers and inverters only

An efficient logic synthesis based on pass-transistor logic (PTL) is developed. Instead of using a static CMOS cell library, which usually contains hundreds of different cells, the PTL synthesizer uses only two types of cells: 2-to-1 multiplexers (MUX) and inverters. The PTL synthesizer first employs the Synopsys design compiler (DC) to perform logic translation and minimization for the input HDL descriptions. Then, the PTL-based technology mapping performs area optimization and driving strength selection considering the user´s area and/or speed requirements. Experiments show that our synthesizer generates results with better area and/or speed performance compared to previous approaches with CMOS or other PTL cell libraries.