Title :
A fringing and coupling interconnect line capacitance model for VLSI on-chip wiring delay and crosstalk
Author_Institution :
Sharp Microelectron. Technol. Inc., Camas, WA, USA
Abstract :
We have developed a fringing and coupling interconnect line capacitance model for accurate circuit simulations, which includes the nonlinearities of second-order effects with field interactions among interconnects. Five actual cases of different surrounding dielectric materials are demonstrated to verify this model with numerical solutions by using 2 and 3 dimensional Poisson equation solver. The propagation delay and crosstalk noise are evaluated in terms of circuit frequency, passivation layer geometry, and packaging material based on the proposed model. The model is also applied to determine the parasitic capacitances among inter-stage interconnects, which are necessary for a precise ring oscillator speed evaluation
Keywords :
VLSI; capacitance; circuit analysis computing; crosstalk; delays; integrated circuit interconnections; integrated circuit modelling; integrated circuit packaging; 2D Poisson equation solver; 3D Poisson equation solver; VLSI onchip crosstalk; VLSI onchip wiring delay; circuit frequency; circuit simulations; coupling capacitance model; crosstalk noise; field interactions; fringing capacitance model; inter-stage interconnects; interconnect line capacitance model; packaging material; parasitic capacitances; passivation layer geometry; propagation delay; ring oscillator speed evaluation; second-order effects; surrounding dielectric materials; Capacitance; Circuit simulation; Coupling circuits; Crosstalk; Dielectric materials; Frequency; Integrated circuit interconnections; Numerical models; Poisson equations; Propagation delay;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541943
