A fringing and coupling interconnect line capacitance model for VLSI on-chip wiring delay and crosstalk

We have developed a fringing and coupling interconnect line capacitance model for accurate circuit simulations, which includes the nonlinearities of second-order effects with field interactions among interconnects. Five actual cases of different surrounding dielectric materials are demonstrated to verify this model with numerical solutions by using 2 and 3 dimensional Poisson equation solver. The propagation delay and crosstalk noise are evaluated in terms of circuit frequency, passivation layer geometry, and packaging material based on the proposed model. The model is also applied to determine the parasitic capacitances among inter-stage interconnects, which are necessary for a precise ring oscillator speed evaluation