Transition time bounded low-power clock tree construction

Power has become a significant issue in clock network design for high-performance ICs because the clock network consumes a large portion of the total power in the system. Also, the clock signal is the signal with the highest frequency in the system, which makes the transition time bound of the clock signal extremely tight. Hence, it is necessary to have transition time bounds to construct low-power clock trees in high performance systems. We formulate the transition time bounded low-power clock tree construction problem. Buffer insertion, buffer sizing and wire sizing are employed to construct the low-power clock tree under a given transition time bound. We propose a top-down dynamic programming algorithm to solve the problem. Experimental results show that the transition time bound has a significant effect on power consumption. Therefore, we need to consider the trade-off between transition time and power consumption in clock tree design. In addition, the short-circuit power´s percentage of the total power is not negligible. Hence, it is not appropriate to neglect it. By carefully considering short-circuit power and transition time of buffers, we get accurate power consumption and transition time compared with SPICE simulation results.