DocumentCode :
3545094
Title :
Explicit delay metric for interconnect optimization
Author :
Ma, Min ; Oulmane, Mourad ; Rumin, Nicholas C.
Author_Institution :
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
fYear :
2005
fDate :
23-26 May 2005
Firstpage :
2453
Abstract :
Interconnect optimization relies heavily on delay metrics which have to be simple yet accurate. This is hard to achieve when the delay is at a point close to the source. We present an explicit metric in which the response at a node is approximated by order reduction to a two-pole circuit using the first 3 moments of the impulse response. The core of the metric is an accurate two-pole, one-zero model which yields the delay. Tests on RC wires and trees demonstrate that our metric is more accurate than the recently published implicit metric WED which uses a statistical interpretation of delay.
Keywords :
approximation theory; circuit optimisation; delays; integrated circuit interconnections; integrated circuit layout; poles and zeros; transient response; trees (mathematics); RC wires; deep submicron designs; explicit delay metric; impulse response; interconnect optimization; order reduction; statistical interpretation; trees; two-pole circuit; Circuit testing; Computer networks; Councils; Delay; Frequency; Integrated circuit interconnections; Poles and zeros; Transfer functions; Weibull distribution; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
Type :
conf
DOI :
10.1109/ISCAS.2005.1465122
Filename :
1465122
Link To Document :
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